Integrated circuits are typically manufactured using photolithography techniques to produce a desired pattern from a photolithographic mask, often referred to as a “photomask,” on a substrate material or wafer. The photomask may be of the type where the circuit pattern is magnified, for example, four or five times. The lithography stepper projects an image of the photomask that is demagnified to the desired size onto a resist coated wafer. In order to amortize the increasing costs of photomasks over multiple circuit patterns or over multiple production stages of the same circuit pattern, it has been proposed to employ photomasks that produce multiple circuit patterns on the same substrate. Similarly, photomasks have been proposed to produce a primary circuit pattern and related supplemental circuitry, such as test and process verification circuitry. A photomask that produces multiple circuits is often referred to as a multi-project (MP) reticle or mask.
It would be expected that during a circuit design verification phase of the product development cycle, all of the various circuit patterns, including any supplemental test circuits be printed from the multi-project mask. That is, the entire photomask field is printed at once. Ultimately, however, one or more of the various circuit patterns may be printed separately by reducing the exposure illumination area (i.e., the field of view) of the lithography stepper to only the portion of the mask that corresponds to the desired circuit pattern. Such a reduction in the illumination area is typically accomplished through the use of framing blades inserted physically up stream of the photomask. In order to accommodate the uncertainty of the framing blade positions that define the limited exposure illumination area, the areas for each circuit pattern on a multi-project mask are surrounded by an opaque region, often referred to as an “exclusion region.” This exclusion region is an area of solid chrome on the photomask and is independent of the tone of the resist to be exposed. The exclusion regions surrounding each pattern area typically have lateral dimensions in the range of 50-300 micrometers on the scale of the wafer (demagnified from the mask scale).
Following the resist exposure of a single pattern area, the exclusion region will typically cause the latent image of the printed circuit pattern to be surrounded by an unexposed region of resist. In a step-and-repeat exposure sequence, subsequent printed patterns are aligned adjacent to the previous ones precisely and the unexposed band adjacent to the previously printed circuit patterns are exposed. Therefore, by “butting” the patterns together on the wafer, the exclusion region around each pattern is overprinted, thereby avoiding a featureless region around each pattern area on the wafer.
For an MP mask, the butting process only avoids printing featureless areas around a pattern area if a single pattern area is printed from the mask. When multiple pattern areas are printed from an MP mask, the exclusion regions will not only be around the printed pattern area but will also lie within the pattern area (separating individual patterns). The exclusion regions that separate the patterns on the mask will leave featureless regions in the resist that will remain after the step-and-repeat printing process. For a positive resist process, the exclusion region will leave band(s) of resist within each repeated area that separate the multiple patterns after resist development. For a negative resist process, the exclusion region will leave band(s) where the resist has been removed after resist development.
Generally, there are design rules that limit, among other things, the pattern density of regions and feature sizes on the wafer to comply with etch and chemical mechanical polish process (CMP) specifications that follow the photolithographic exposure steps. It has been found that when printed, the exclusion regions on multiple project masks may have a harmful affect on some etch processes, including etch and chemical mechanical polishing process. When the various circuit patterns (including any supplemental test circuits) are printed from the multi-project mask during, e.g., the circuit design verification phase, the exclusion regions violate critical design rules. Thus, the multi-project masks may cause design rule violations when multiple patterns are printed from the mask and make it difficult to verify critical process steps, thereby defeating the initial motivation to use the multi-project masks.
It is advantageous if a method for manufacturing multiple circuit patterns (or a primary circuit pattern and related supplemental circuitry) used the same multi-project mask to print multiple circuit patterns during a circuit design phase or process verification phase and to selectively print individual circuit patterns during a production phase. A need therefore exists for a method for manufacturing multiple circuit patterns (or a primary circuit pattern and related supplemental circuitry) that overcomes the above problems and limitations of the prior art.